Electrical Engineers

• Slide rule + hand calculation + physica…1884–1920

  Slide rule + hand calculation + physical prototyping (electrification era)

  The first electrical engineers designed dynamos, transformers, and transmission lines using slide rules, logarithm tables, and Maxwell's equations worked out by hand on drafting paper. Circuit analysis required solving systems of differential equations analytically — no numerical methods, no simulation. Physical prototyping was the only verification: you built the thing and measured it. The 1893 Chicago World's Fair, where Westinghouse ran 100,000-watt AC generators to light the entire exposition, was simultaneously an engineering triumph and an engineering test — Nikola Tesla and Charles Steinmetz designed the system on paper, then ran it at full load for the first time at the Fair itself.

  Effect on the work

  The cohort was tiny (~2,000-5,000 US practitioners in 1900) but extraordinarily productive per person — a small team of engineers at Edison General Electric or Westinghouse could design power systems serving tens of thousands of customers.

• Vacuum tube + graphical network analysis1920–1947

  Vacuum tube + graphical network analysis (power system era)

  The triode vacuum tube (Lee de Forest, 1906) gave electrical engineers an amplifying device for the first time — enabling long-distance telephony, radio broadcast, and electronic instrumentation. Simultaneously, R.H. Steinmetz's work on AC circuit analysis (phasor notation, published 1893-1897) gave power-systems engineers the mathematical tools to design transmission systems analytically rather than empirically. By the 1930s, AC network analyzers — room-sized scale models of power grids wired with scaled resistors and transformers — let engineers simulate regional power-flow behavior before committing to physical infrastructure. The slide rule remained the primary computational instrument; complex calculations were "checked" by the network analyzer, not replaced by it.

• Transistor + early digital computing1947–1970

  Transistor + early digital computing (Bell Labs, Texas Instruments era)

  On December 23, 1947, John Bardeen and Walter Brattain demonstrated the first point-contact transistor at Bell Labs, replacing the vacuum tube's filament, glass envelope, and high operating temperature with a solid-state switch the size of a fingertip. Shockley's junction transistor (1951) made commercial production practical. Within a decade, the transistor had created an entirely new sub-discipline — solid-state electronics — and the professional identity of electrical engineering began to split into power/systems engineers (who continued working with AC machinery and distribution) and semiconductor/electronics engineers (who worked with transistor circuits). Texas Instruments put the transistor on the market in 1954; by 1960 the vacuum tube was in commercial retreat. Jack Kilby at TI demonstrated the first integrated circuit on September 12, 1958; Robert Noyce at Fairchild developed the practical monolithic IC shortly after.

  Effect on the work

  The transistor revolution created demand for a new kind of electrical engineer — one trained in quantum mechanics and materials science, not just circuit theory. University EE departments bifurcated. IEEE membership grew rapidly as the transistor-trained generation entered the profession.

• IEEE unification + SPICE circuit simula…1963–1985

  IEEE unification + SPICE circuit simulation (analog and digital design era)

  The 1963 merger of the AIEE and IRE into the IEEE created the professional infrastructure — a single standards body, a single publication network, a single credentialing umbrella — for what was now a 300,000-member profession. Simultaneously, the SPICE circuit simulator (Simulation Program with Integrated Circuit Emphasis, developed at UC Berkeley by Laurence Nagel, first released 1972) gave analog and mixed-signal circuit designers the ability to numerically simulate circuit behavior before fabrication — replacing the build-and-measure cycle for small-signal analysis. SPICE became the standard verification step for analog circuit design and remains in active use as of 2025.

  Effect on the work

  SPICE did not reduce engineering headcount — it expanded what each engineer could design. Circuits that would have taken months of iteration to validate on the bench could be verified in days on a workstation. The size of feasible designs scaled up faster than the workforce; the engineer became a lever on simulation, not a reducer.

• Commercial EDA1981–1999

  Commercial EDA — Cadence (1988), Synopsys (1986), Verilog/VHDL HDLs

  Electronic design automation moved from academic simulators to commercial products in 1981 when Daisy Systems, Mentor Graphics, and Valid Logic Systems (the "DMV" companies) introduced workstation-based schematic capture and simulation. Synopsys was founded in 1986 by Aart de Geus and co-founders (originally as Optimal Solutions); Cadence Design Systems took its current form in 1988 from a merger of SDA Systems and ECAD. Verilog (1986) and VHDL (1985, DoD-mandated) gave chip designers hardware description languages — the ability to specify chip behavior as code rather than as drawn schematics. The first EDA trade show ran at the Design Automation Conference in 1984. By the mid-1990s, EDA tools had made it possible to design multi-million-transistor ASICs in a software environment, outsourcing fabrication to foundries (TSMC founded 1987, the first pure-play fab). The VLSI design engineer emerged as a distinct role.

  Effect on the work

  EDA tools raised the transistor-per-engineer ratio by multiple orders of magnitude — a small team could design chips that previously required hundreds of engineers to lay out manually. Total EE employment contracted in sectors where EDA-enabled productivity outran demand; it expanded in sectors where lower design cost created entirely new product categories.

• MATLAB/Simulink + CAD/CAE power tools +…1999–2019

  MATLAB/Simulink + CAD/CAE power tools + offshore foundry model (systems integration era)

  The 2000s established the modern split in electrical engineering work: chip-design engineers working in EDA environments (mostly offshore in Korea, Taiwan, and increasingly China), and systems-level electrical engineers who specified power, control, and signal-integrity requirements for complete products — using MATLAB/Simulink for control-system design and simulation, ANSYS Maxwell for electromagnetic field analysis, and PSpice/LTspice for power-electronics simulation. The "fabless" model (AMD, Qualcomm, Nvidia all fab-less by the 2000s) made chip design a software-intense activity while moving fabrication engineering offshore. Power electronics — motor drives, switching power supplies, inverters — became the domain of US electrical engineers who stayed domestic, as infrastructure and heavy industry proved harder to offshore than semiconductor manufacturing.

• AI-assisted EDA2020–2023

  AI-assisted EDA — Synopsys DSO.ai (2020) + Cadence Cerebrus (2021)

  In 2020, Synopsys introduced DSO.ai (Design Space Optimization AI), a reinforcement-learning system for automatic chip physical implementation — place and route optimization that previously required experienced layout engineers iterating manually over days or weeks. Cadence followed in 2021 with Cerebrus, a machine-learning system that optimizes the digital design flow end-to-end using RL. Both products were the first commercial AI tools to automate parts of chip design that had required senior engineer judgment. Google had published a Nature paper in June 2021 showing that an AI system could place chip floorplans faster than human experts — accelerating the commercial competition. By 2022, both Synopsys and Cadence were marketing AI-in-the-loop design flows as their primary value proposition over competitors.

  Effect on the work

  DSO.ai and Cerebrus reduced the iteration time for physical implementation by 10-20× in vendor-reported benchmarks; they did not eliminate the EE's role but changed it from "manually tuning the placer" to "specifying constraints and interpreting AI-generated solutions." Senior chip-layout engineers faced the first real productivity displacement from AI in this era.

• CHIPS Act + AI-datacenter power systems…2022–present

  CHIPS Act + AI-datacenter power systems + IRA electrification (infrastructure super-cycle)

  Three simultaneous policy-and-capital shocks reshaped the demand picture for US electrical engineers in 2022-2025: (1) CHIPS and Science Act (August 9, 2022): $52.7B in semiconductor manufacturing subsidies; TSMC committed to a second Arizona fab (announced $6.6B federal grant post-passage), Intel secured $8.5B for Ohio and Arizona, Samsung received $6.4B for Texas. BLS projects semiconductor fabrication employment growing 15.1% 2024-34. Each new fab requires hundreds of process and facilities electrical engineers for three to five years of construction. (2) AI datacenter buildout: Microsoft announced $80B+ in AI infrastructure spending for FY2025; Meta committed $60B+ in 2025; Amazon committed $100B+ across multi-year datacenter expansion. A hyperscale datacenter at 100MW of critical IT load requires tens of millions of watts of power distribution infrastructure — medium-voltage switchgear, UPS systems, backup generation, grounding systems — that must be designed by electrical engineers with PE licenses. BLS projects solar electric power generation employment growing 184% and wind 79.7% through 2034, both of which require grid-interconnection electrical engineering. (3) Inflation Reduction Act (August 16, 2022): $369B in climate provisions, including ITC extensions for solar, EV charger credits, heat pump incentives. Grid modernization for bidirectional residential power flows (rooftop solar, vehicle-to-grid) requires distribution-system electrical engineers to redesign protection coordination, power quality, and control systems that were designed for one-directional power flow. In parallel, Synopsys launched Synopsys.ai Copilot in November 2023 — an LLM-based generative AI assistant for chip design, built on OpenAI models via Microsoft — and presented a five-level autonomy roadmap toward fully autonomous chip design at the March 2025 SNUG conference.

  Effect on the work

  BLS National Employment Matrix projects +7.2% growth for 17-2071 (192,000 → 205,700) over 2024-34, with the strongest growth in solar (+184%), wind (+79.7%), and semiconductor manufacturing (+15.1%) subsectors. The solar and wind numbers are small in absolute terms (1,200 and 400 engineers respectively); the datacenter power-systems and semiconductor-fab demand is larger and structurally sustained through at least 2030.

What's changing in your day

Three parts of your work where AI is already doing real lifting, and what stays yours.