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Electronics Engineers, Except Computer

Scrub through 124years of this role's history, from when it first emerged, through every wave of technology that reshaped it, to the cited projections for where it's heading next.

2026drag to travel through time
1925195019752000now
2026
Known today as Electronics Engineers, Except Computer (BLS SOC 17-2072)
Latest actual · 2024
96K
BLS OEWS May 2024, sourced from O*NET which reflects the same BLS establishment-survey figure. Electronics engineers excluding computer is now a substantially smaller workforce than in 2002, reflecting the sustained long-term shift of consumer electronics manufacturing to Asia (reducing domestic design staff) and the reclassification of many formerly "electronics engineer" roles into computer hardware engineering (15-1252) as digital design absorbed increasing shares of hardware work. The remaining workforce is concentrated in aerospace and defense electronics, medical device hardware, telecommunications infrastructure, and industrial electronics, sectors that require US-based engineers for security clearance, regulatory, or supply-chain reasons.
Latest actual · 2024
$127,590
Source: BLS-OEWS
Each dot is a cited figure over time; the dotted line only links them (values between aren't measured). Hollow dots are estimates.
Tools of the era

The tools that defined the work

Select an era to see how it reshaped the work.

  • Vacuum tube circuits and graphical design methods

    The first electronics engineers designed entirely with vacuum tubes: triodes, tetrodes, pentodes, and magnetrons. Their design tools were graphical: characteristic curves plotted on paper, load lines drawn by hand, and Smith charts (invented by Phillip Hagar Smith at Bell Labs in 1939) for impedance matching. Circuit analysis used Maxwell's equations, transmission-line theory, and the nascent network theory that MIT's Vannevar Bush and Bell Labs' Harry Nyquist and Claude Shannon were developing in the 1920s-1940s. Slide rules handled numerical computation. The vacuum tube limited electronics to room-temperature, high-voltage, high-power, bulky equipment, but it enabled radar, broadcast radio, long-distance telephony, and the first electronic computers.

    Effect on the work

    The vacuum tube era required large teams of engineers for even modest systems: the MIT Radiation Laboratory employed over 4,000 people by 1945 working on radar systems that would today be designed by a handful of engineers using simulation software. High labor intensity per circuit function was a structural feature of the era.

    Work toolChanging equipment
  • Transistor and discrete solid-state components

    William Shockley, John Bardeen, and Walter Brattain demonstrated the point-contact transistor at Bell Labs on December 23, 1947. Texas Instruments produced the first commercial silicon transistor in 1954. The transistor replaced the vacuum tube for most signal-amplification and switching functions within fifteen years: it operated at lower voltage, consumed less power, generated less heat, and was far smaller and more reliable. For electronics engineers, the transistor both simplified and complicated the job. Circuits became smaller and more numerous, demanding tighter understanding of device physics (minority carrier injection, base-emitter biasing, junction capacitance) that the vacuum tube's macro-scale behavior had not required. By 1960 the first transistorized consumer radios, hearing aids, computers, and military avionic systems were in production, and electronics engineers needed fluency in both device physics and circuit topology.

    Effect on the work

    The transistor dramatically increased what one engineer could accomplish per unit of time: a transistor radio contained perhaps 6-10 transistors where a comparable vacuum tube design would have used 5-8 tubes with much larger support circuitry. This amplified the engineer's design reach without immediately reducing headcount, as demand for new electronics products expanded faster than per-engineer productivity improved.

    Work toolChanging equipment
  • Integrated circuits (Kilby/Noyce 1958-59) and early SPICE simulation

    Jack Kilby built the first working integrated circuit at Texas Instruments on September 12, 1958, using germanium with gold wire bonds; Robert Noyce of Fairchild independently conceived the planar monolithic IC in 1959, which became the commercial standard. The IC meant that an electronics engineer could design a chip containing dozens, then hundreds, then thousands of transistors and have them fabricated in silicon simultaneously. SPICE (Simulation Program with Integrated Circuit Emphasis) was developed at UC Berkeley in 1972 and by the late 1970s was running on institutional computers, giving engineers the first analytical tool that could simulate complex transistor-level circuits numerically rather than by hand. The IC era transformed the electronics engineer's vocabulary: instead of selecting off-the-shelf components and wiring them together, engineers increasingly worked at the level of topologies, architectures, and system-level integration. The analog circuit design canon, which Bell Labs engineers had built up through the 1950s and 1960s, was codified in textbooks by Sedra, Smith, Razavi, and others that are still in use today.

    Effect on the work

    Integrated circuits allowed enormous complexity to be achieved by a small engineering team, but also opened product categories (minicomputers, electronic instruments, early medical monitors) that did not previously exist. Employment of electronics engineers expanded substantially through the 1960s and 1970s as ICs enabled entirely new product markets rather than simply replacing older designs.

    Work toolChanging equipment
  • EDA workstations: Cadence, Mentor, Synopsys, and personal computer simulation (SPICE on PC)

    Electronic Design Automation arrived as a commercial category in the mid-1980s when Sun Microsystems and Apollo Computer workstations became affordable enough for engineering departments. Cadence Design Systems (founded 1988 from the merger of SDA Systems and ECAD) and Mentor Graphics (founded 1981) industrialized schematic capture, PCB layout, and analog simulation on workstation platforms. SPICE migrated from shared mainframes to individual engineering workstations by 1985, and to personal computers by 1990 (PSpice, the PC port, had its first commercial release in 1984). By 1995 an electronics engineer had a personal workstation capable of simulating circuits that would have required an institutional computing center a decade earlier. PCB layout moved from physical tape-up (called "taping out" literally, with adhesive tape on Mylar) to interactive graphical layout on-screen. For the first time, a single engineer could go from concept to verified schematic to routed board to fabrication-ready Gerber files without leaving their desk.

    Effect on the work

    EDA workstations substantially increased per-engineer productivity and enabled smaller teams to design more complex products. They did not reduce the engineering workforce in absolute terms through the 1980s-1990s, because demand for new electronic products expanded faster than per-person throughput increased. The real employment-shrinking effect came after 2001 when Asian manufacturing absorbed the consumer-electronics design work that had employed large US engineering teams.

    Work toolChanging equipment
  • Modern EDA platforms: HFSS, ADS, Virtuoso (3D EM simulation and RF-aware design)

    The 2000s saw RF and microwave simulation move from an academic specialty to a standard engineering workflow tool, driven by cellular telephony (the 2G-to-3G-to-4G transition created enormous demand for RF engineers) and the Wi-Fi/Bluetooth boom. Ansys HFSS (High Frequency Structure Simulator), acquired by Ansoft which Ansys bought in 2008, became the industry standard for 3D EM simulation of antennas, RF cavities, and waveguide components. Keysight's Advanced Design System (ADS), developed from the HP Microwave Design System of the 1980s, became the standard for RF circuit design and system-level link budget simulation. Cadence's Virtuoso platform, with its Spectre SPICE simulator, became the dominant environment for custom analog and RF IC design at foundries worldwide. These tools required weeks of training to use effectively, raising the specialization floor for RF and analog engineers and creating a recognizable skill taxonomy: ADS for microwave, HFSS for EM, Virtuoso/Spectre for analog IC, Cadence Allegro or Mentor PADS for PCB.

    Effect on the work

    The specialized EDA toolchain of the 2000s concentrated electronics engineering employment in companies and roles that could justify the tool licensing costs, which ran $50,000 to $200,000+ per seat annually. This favored large defense primes, semiconductor companies, and well-funded startups over small design shops. US electronics engineering employment continued declining as consumer electronics design migrated to Asia, but the defense, aerospace, and medical device sectors held steady because ITAR controls, FDA clearance requirements, and DO-160 qualification regimes kept design work onshore.

    Work toolChanging equipment
  • Cloud EDA, model-based design, and AI-assisted DRC (Altium 365, Cadence cloud, Keysight cloud)

    Cloud computing changed how EDA licenses were purchased and deployed, but more importantly enabled multi-site collaboration on electronic designs for the first time without expensive file-transfer workflows. Altium 365, launched in 2020 as a cloud-connected PCB design platform, allowed global teams to share live schematic and layout data, check supply-chain availability of components against real-time distributor stock, and manage design revisions in a version-controlled environment. Keysight moved PathWave to a cloud-hosted subscription model. Cadence offered cloud-bursting for simulation jobs too large for local workstations. AI began appearing as a feature within existing tools: Altium added AI-powered component recommendation based on historical design choices and supply chain data; Cadence began embedding machine-learning-based design rule checking. This era set the infrastructure for the more dramatic AI-native tooling that arrived 2023-2026.

    Work toolChanging equipment
  • AI-native EDA: Cadence Allegro X AI, HFSS Engineering Copilot, Keysight PathWave AI Engine, Spectre AI

    Between 2023 and 2026 the major EDA vendors embedded generative AI and machine-learning optimizers directly into the tools electronics engineers use daily. Cadence Allegro X AI compresses a three-day PCB placement task to 75 minutes with a 10x turnaround improvement. Ansys HFSS 2026 R1 delivers 17x faster radiation pattern simulation for antenna design. The Ansys Engineering Copilot (2025 R2) allows natural-language setup of simulation scenarios across HFSS, Maxwell, and Fluent. Keysight's PathWave AI Engine automates load-pull optimization for power amplifier design, collapsing weeks of Smith-chart iteration to hours. Cadence Spectre AI accelerates analog Monte Carlo and process-corner simulations in Virtuoso Studio. Bloomberg Intelligence projects AI adds $6 billion to the EDA market through 2030 at 15-20%+ CAGR. The AI tooling wave does not eliminate the electronics engineer's job: it eliminates the most tedious iterative work (placement iteration, matching network sweep, simulation corner coverage) while leaving the high-judgment decisions intact. Regulatory sign-off (FCC, IEC 60601, DO-160), RF architecture definition, hands-on lab bring-up, and failure analysis remain firmly human.

    Effect on the work

    The AI EDA wave is projected to increase per-engineer throughput substantially without immediately reducing headcount, similar to the effect of SPICE workstations in the 1980s. Whether it eventually reduces team size depends on whether AI-accelerated speed generates proportional new product demand. The 5G/6G infrastructure rollout, EV power electronics, and defense modernization programs appear likely to absorb the productivity gain as faster development cycles rather than smaller teams, at least through 2034.

    AI audit toolsPattern detection
Projection cone · present → 2034

What credible sources project

Scrub the slider past now to anchor each scenario on the scrubber. The spread is the range of futures credible sources project for this role.

Employment outlook
Projected change in the number of people doing this work.
BLS Occupational Outlook Handbook 2025-26 — Electrical and Electronics Engineers
2034
+7%
BLS Occupational Outlook Handbook 2025-26 edition reports 7% projected employment growth for the combined electrical and electronics engineers category from 2024 to 2034, described as "much faster than average." The OOH specifically cites increasing demand for AI-related products and infrastructure, next-generation wireless communications (5G/6G), autonomous vehicle sensors and controls, and continued defense modernization as the primary demand drivers. This OOH figure covers both 17-2071 (Electrical Engineers) and 17-2072 (Electronics Engineers, Except Computer) as a combined grouping; the 17-2072 specific projection from the National Employment Matrix (6.2%) is slightly below the combined 7% because electrical engineers (17-2071) are benefiting from the EV/grid/AI-data-center power boom which is growing the electrical segment faster than electronics.
BLS National Employment Matrix 2024-34
2034
+6.2%
BLS National Employment Matrix 2024-34 projects electronics engineers (17-2072) employment to grow from 95.9 thousand (2024) to 101.8 thousand (2034), a 6.2% increase (+6,000 positions). The overall BLS 2024-34 projection for electrical and electronics engineers combined is 7%, described as "faster than average." Growth is driven by 5G/6G wireless infrastructure buildout, continued demand in aerospace and defense electronics, medical device hardware design, EV power electronics and charging infrastructure, and AI data center power distribution. The projection assumes that AI EDA tools increase per-engineer throughput but that product demand scales proportionally through the decade, keeping headcount modestly positive.
AI task exposure
Share of the role’s tasks that researchers estimate AI can do. This is a measure of task exposure, not a forecast of jobs lost.
Eloundou et al. "GPTs are GPTs" (2023)
2028
58%
of tasks
GPT-4 task-by-task LLM exposure labeling on O*NET tasks for Architecture and Engineering occupations. Electronics engineers score at approximately 58% theoretical LLM task exposure, reflecting the substantial share of documentation, report-writing, specification authoring, code review, and mathematical analysis tasks that LLMs can meaningfully assist. Critically, the AI Changing Work analysis notes observed exposure in the electronics engineering workforce is around 25%, well below the theoretical ceiling, because the dominant employers (defense contractors, medical device OEMs, aerospace primes) operate under ITAR controls, FDA change-control regimes, and DO-160/MIL-SPEC qualification requirements that slow AI adoption. The physical-world tasks, regulatory sign-off tasks, and hands-on lab characterization tasks are unmoved by LLM exposure: an LLM cannot calibrate a VNA or sign the FCC technical construction file.
Today, in this role

What's shifting in the work right now

The historical view above shows how this role has moved. This is the present-day detail: which AI tools are picking up which tasks, where the edge still is, and the natural directions this work can grow.

What's changing in your day

Three parts of your work where AI is already doing real lifting, and what stays yours.

AI is sitting alongside you hereDesign and lay out mixed-signal and RF printed circuit boards using Cadence Allegro X AI or Altium 365 AI Copilot: define stackup, impedance targets, RF trace geometry, and power island isolation strategy

Design and lay out mixed-signal and RF printed circuit boards using Cadence Allegro X AI or Altium 365 AI Copilot: define stackup, impedance targets, RF trace geometry, and power island isolation strategy; use AI global placement to evaluate thousands of component arrangements for signal integrity, RF isolation, and thermal management simultaneously; review AI-generated placement for critical analog-to-digital return current paths, RF shielding effectiveness, and assembly-process constraints before routing sign-off.[7],[9]

Where your edge is

Allegro X AI compresses three-day PCB placement tasks to 75 minutes, but AI placement optimizes for wire-length and DRC clearance — it does not model RF isolation, EMC partition effectiveness, or the grounding return current paths that determine whether a mixed-signal board meets its spurious-free dynamic range specification. Build a pre-placement RF partition checklist — ground plane splits, RF shielding walls, digital keepout zones around ADC reference planes — so your AI-generated layout review is structured and systematic rather than an ad-hoc EMC search.

AI is sitting alongside you hereDesign and simulate RF/microwave circuits — low-noise amplifiers (LNAs), power amplifiers (PAs), mixers, voltage-controlled oscillators (VCOs), and matching networks — using Keysight PathWave ADS with its AI-guided harmonic balance and load-pull automation: specify noise figure, gain, IP3, and P1dB targets

Design and simulate RF/microwave circuits — low-noise amplifiers (LNAs), power amplifiers (PAs), mixers, voltage-controlled oscillators (VCOs), and matching networks — using Keysight PathWave ADS with its AI-guided harmonic balance and load-pull automation: specify noise figure, gain, IP3, and P1dB targets; let the AI optimizer sweep matching topology and component values across the Smith chart; validate AI-proposed matching network against measured S-parameter data before committing to PCB layout.[6]

Where your edge is

PathWave ADS AI automation compresses Smith-chart matching iterations from days to hours, but the optimizer works within the topology you specify — choosing between a two-element L-match, a three-element pi-network, or a transmission-line topology for your substrate and frequency band requires physical intuition about parasitics, thermal cycling, and manufacturing tolerance that the optimizer cannot model. Build deep S-parameter and noise-figure measurement skills so you can validate AI-generated matching results against bench measurements before committing a design to PCB.

AI is sitting alongside you hereModel and simulate antenna systems, RF filters, waveguide components, and electromagnetic compatibility (EMC) compliance scenarios using Ansys HFSS with the 2026 R1 GPU-accelerated solver and Engineering Copilot: use the Copilot to configure antenna simulation geometry via natural language, run GPU-parallelized radiation pattern sweeps at 17x the speed of prior solvers, and interpret far-field gain, impedance, and SAR predictions for 5G mmWave or aerospace antenna arrays

Model and simulate antenna systems, RF filters, waveguide components, and electromagnetic compatibility (EMC) compliance scenarios using Ansys HFSS with the 2026 R1 GPU-accelerated solver and Engineering Copilot: use the Copilot to configure antenna simulation geometry via natural language, run GPU-parallelized radiation pattern sweeps at 17x the speed of prior solvers, and interpret far-field gain, impedance, and SAR predictions for 5G mmWave or aerospace antenna arrays; validate AI-accelerated results against anechoic-chamber measurements before EMC pre-scan.[4],[5]

Where your edge is

HFSS 2026 R1 accelerates radiation pattern simulation 17x, but simulation accuracy depends critically on geometry fidelity, dielectric loss model accuracy, and correct boundary conditions at connector and cable interfaces — factors the Copilot cannot validate for you. Build a structured benchmark practice: before trusting AI-accelerated parametric sweeps for a new antenna topology or substrate, validate against a known analytical closed-form or published measurement to confirm your material model and mesh density are correct.

Where this role is heading

Natural next steps for someone with your foundation: not exits, evolutions.

A direction you could grow

Architectural and Engineering Managers

Senior Electronics Engineers who build program management, vendor governance, and AI tool evaluation skills are well-positioned to move into Engineering Manager roles overseeing hardware programs. This transition is especially timely: organizations in defense electronics, medical devices, consumer wireless, and telecom infrastructure all need managers who understand both the technical domain (RF, analog, mixed-signal) and the AI EDA toolset reshaping how designs are executed. Engineering Managers retain technical credibility while operating at budget, headcount, and roadmap scope where AI displacement pressure is minimal. Bloomberg Intelligence projects AI adds $6B to the EDA market through 2030 — organizations need engineering leaders who can evaluate these tools and build team capability. BLS projects strong demand for engineering managers tied to electronics and semiconductor investment.

What you'd add
  • · Hardware program management: milestone planning for multi-phase product development (concept, prototype, DVT, PVT), certification schedules for FCC/IEC/DO-160, supplier qualification timelines
  • · AI tool evaluation and governance: building team standards for when AI-generated simulation results may be used to make design-commit or regulatory-submission decisions
  • · Regulatory strategy: managing FCC, FDA 510(k)/De Novo, and DO-160 certification programs; coordinating with notified bodies and test laboratories
  • · People management: hiring RF, analog, and embedded engineers; technical interview design; career development for specialists
  • · Executive communication: translating RF compliance margin, EMC re-test risk, and silicon revision costs into portfolio-level business impact
What it takesSome new skills to pick up
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The data behind this timeline

On record since1912
Latest tracked employment95,900 (US, 2024)
Latest median pay$127,590 (2024)
Outlook+6.2% by 2034 (BLS National Employment Matrix 2024-34)
View all 27 cited data points
YearUS employmentMedian annual paySource
194030,000n/aESTIMATE
1950100,000n/aESTIMATE
1963180,000n/aESTIMATE
1997n/a$61,200ESTIMATE
2002173,000n/aESTIMATE
2003137,320$71,370BLS-OEWS
2004135,560$75,770BLS-OEWS
2005130,050$78,030BLS-OEWS
2006131,880$81,050BLS-OEWS
2007133,870$83,340BLS-OEWS
2008139,930$86,370BLS-OEWS
2009135,990$89,310BLS-OEWS
2010133,660$90,170BLS-OEWS
2011136,310$91,500BLS-OEWS
2012134,960$91,820BLS-OEWS
2013135,350$94,250BLS-OEWS
2014133,990$95,790BLS-OEWS
2015135,390$98,270BLS-OEWS
2016132,100$99,210BLS-OEWS
2017134,930$102,180BLS-OEWS
2018134,110$102,700BLS-OEWS
2019128,800$105,570BLS-OEWS
2020122,320$107,540BLS-OEWS
2021107,170$104,820BLS-OEWS
2022106,640$108,170BLS-OEWS
202396,410$119,200BLS-OEWS
202495,900$127,590BLS-OEWS
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